1. Field of the Invention
The present invention relates generally to a circuit and method for compensating for variation in an offset voltage depending on variation in temperature in a photodiode integrated circuit and, more particularly, to a circuit and method capable of compensating for variation in an offset voltage depending on variation in surrounding temperature by adding a circuit for varying currents flowing through bipolar junction transistors, the characteristics of which varies with variation in surrounding temperature, according to variation in temperature.
2. Description of the Related Art
Recently, optical storage technology is developing toward high density, high speed and compactness in technical competition with memory, hard disk and magnetic disk technology, and the importance of the optical storage technology is increasing due to advantages over other storage technologies.
Such optical storage technology uses a method in which a disk drive and a storage medium (that is, an optical disk) are detachably attached to each other. The storage medium has advantages in that it can be implemented at low cost compared to other storage media, and data can be permanently stored thereon. In particular, the durability of the optical storage medium against temperature and impact is known to be excellent compared to that of other storage media.
However, the optical storage technology is disadvantageous in that its transmission rate is low and its storage capacity is low. To overcome the disadvantages, high-capacity and high-speed optical storage technologies rivaling a magnetic disk have recently been developed with rapid technological advances. Currently, research into a PhotoDetector Integrated Circuit (PDIC), that is, one of optical storage technologies, is being conducted.
FIG. 1 is a schematic diagram of a typical PDIC.
As shown in FIG. 1, the PDIC generates a current Iph when light is incident on a light-receiving element, for example, a photodiode 10. The current Iph is converted into a voltage and is amplified by a current-voltage conversion amplifier 20 and a feedback resistor RF, so that an output voltage VOUT is output.
When an input optical signal is 0, that is, when an optical signal input to the photodiode 10 does not exist, the output voltage VOUT must be 0 V ideally. However, a current flows from the inverting and non-inverting input terminals of the current-voltage conversion amplifier 20, and a voltage that is applied to the feedback resistor RF appears at an output terminal, so that the output voltage VOUT is not 0. In this case, the applied voltage is referred to as an offset voltage.
In the prior art, to compensate for such an offset voltage, a method of compensating for the offset voltage by reducing the magnitude of an offset current flowing from the inverting and non-inverting input terminals is used.
As an example, FIG. 2 shows the construction of a conventional current-voltage conversion amplifier 20 including a compensation circuit 21.
The current-voltage conversion amplifier 20 has a non-inverting input terminal (+) and an inverting input terminal (−). A reference character RF of FIG. 1 corresponds to a feedback resistor. Metal-Oxide-Silicon Field Effect Transistors (MOSFETs) P7 and P8 constitute an active resistor 24. A capacitor C1 is a circuit element for compensating for frequency characteristics.
When no optical signal is incident on the photodiode that is connected to the non-inverting input terminal (+), an offset current IB1 flowing from the base terminal of a transistor Q1, which is a Bipolar Junction Transistor (BJT), generates the offset voltage.
For convenience of description, it is assumed that the magnitude of the offset current flowing from the non-inverting terminal (+) is 1 μA. Constant current values of 100 μA, 50 μA and 50 μA are set on MOSFETs P1, P2 and P3, respectively, by a bias stage.
Accordingly, when constant currents IC1 and IC2 flowing through transistors Q1 and Q2, which are identical BJTs, each are 50 μA, and the amplification factor of the transistor Q1 is 50, the offset current IB1 is 1 μA. That is, when the compensation circuit does not exist, the offset current IB1 is 1 μA.
Meanwhile, the current I1 of 50 μA flowing through the MOSFET P3 also flows through a transistor Q3. Assuming that the amplification factor of the transistor Q3 is 50, the base current IB4 of the transistor Q3 is 1 μA. A current division unit 23 is composed of current mirror circuits, and the MOSFETs P4 and P5 and MOSFETs P4 and P6 constitute two pairs of current mirrors. In the current division unit 23, a current IB3 flowing through the MOSFET P4 is divided into halves of the current IB3, that is, 0.5 μA, and is then mirrored. The mirrored currents 0.5 μA are applied to the non-inverting input terminal (+) and the inverting input terminal (−), and the current compensates for the offset current IB1, so that the current of the base terminal of the transistor Q1 is 0.5 μA.
Since the compensation current is 0.5 μA and the current flowing from the non-inverting input terminal (+) is 1 μA, the offset current is 0.5 μA.
The offset voltage VOUT is affected by the magnitude of the offset current IB1, and the magnitude of the offset current BI1 is reduced by the compensation circuit 21. As a result, variation in the output voltage VOUT, which is affected by the magnitude of the offset current, decreases even though variation occurs due to arbitrary factors.
Meanwhile, of the elements constructing the current-voltage conversion circuit 22, BJTs O1, Q2 and Q4 have base-emitter voltages that are affected by variation in surrounding temperature, so that the base-emitter voltage VBE decreases by about 2 mV whenever the surrounding temperature increases by 1° C., and the base-emitter voltage VBE increases by 2 mV whenever the surrounding temperature decreases by 1° C.
The case of the transistor Q4 is described below. When the surrounding temperature increases, the current IC4 flowing through the transistor Q4 is constant at 50 μA because the base-emitter voltage VBE of the transistor Q4 decreases and the current IC4 is fixed at 50 μA by a bias applied to the MOSFET P2 regardless of the variation of the base-emitter voltage VBE, so that the output voltage VOUT increases.
In contrast, when the temperature decreases, the base-emitter voltage VBE of the transistor Q4 increases, and the current IC4 flowing through the transistor Q4 is constant at 50 μA, so that the output voltage VOUT decreases.
As described above, when the output voltage varies, the operation of the circuit, which is designed to be optimized for a constant offset voltage, is affected by variation in surrounding temperature.
As shown in FIG. 2, the circuit having the conventional compensation circuit 21 does not directly compensate for variation in the offset voltage depending on variation in surrounding temperature, and only reduces the magnitude of the offset current in proportion to the offset voltage, thus causing only an effect of reducing the variation in the offset voltage depending on variation in temperature.
In the circuit including the BJTs, a compensation circuit, which allows a constant operation regardless of the variation in temperature by compensating for the variation in the magnitude of the output voltage generated depending on variation in surrounding temperature, is required.
In relation to such a compensation circuit, Japanese Unexamined Pat. Pub. No. 11-68476 discloses a scheme of correcting an offset voltage by applying an offset setting voltage to the substrate of a MOSFET that constitutes a differential amplifier as an example of a scheme for compensating an offset voltage.
Although the disclosed scheme may be a next best measure for compensating for operational variation depending on variation in temperature, it does not provide a direct solution to the problem caused by variation in the operational value of elements depending on variation in temperature.